The development of a computer graphics system creates the need for fast memories capable of storing huge amounts of data, such as 3-D graphics data. Among such memories are cached memories developed to improve DRAM main memory performance by utilizing a faster SRAM cache memory for storing the most commonly accessed data. For example, U.S. Pat. No. 5,566,318 discloses an enhanced DRAM that integrates a SRAM cache memory with a DRAM on a single chip. Sense amplifiers and column write select registers are coupled between the SRAM cache and the DRAM memory array. A column decoder is associated with the SRAM cache for providing access to the desired column of the SRAM. A row decoder is associated with the DRAM memory array to enable access to particular rows of the DRAM. Input/output control and data latches receive data from the SRAM to provide data output via data input/output lines. The current row of data being accessed from the DRAM memory array is held in the SRAM cache memory. Should a cache "miss" be detected, the entire cache memory is refilled from the DRAM memory array over a DRAM-to-cache memory bus.
As a way of improving speed and performance of a RAM, a dual-port RAM has been developed which enables two separate input/output ports to access the memory array. However, the dual-port RAM cannot provide effective control of data input and output, because its ports are not interchangeable. For example, data traffic cannot be redistributed between the ports, when one of them is overloaded and the other is underloaded.
Accordingly, it would be desirable to provide a multi-port RAM chip having interchangeable ports.
Also, it would be desirable to provide a multi-port RAM which would be fully functional through one port if the other port is disabled.
Further, the dual-port RAM provides an external device, such as a graphics controller, with only write or read access to the memory array at one time. For example, one port cannot provide reading data from the memory array, while the other port being used for writing data to the memory array.
It would be desirable to provide a multi-port RAM that allows read and write accesses from different ports to be performed simultaneously.
Also, it would be desirable to enable a multi-port RAM to combine its two input/output ports into a single input/output port twice as wide as each port of the RAM.